1. Field of the Invention
The present invention relates to the layout of a transistor, particularly to the layout of a Thin Film Transistor (TFT) and the method of implementing the same.
2. Description of the Prior Art
In electronic products nowadays, the using of transistors often comes in the type of an array instead of a single one, for example, the memory array shown in FIG. 1A, comprising the conducting lines 11 and the conducting lines 12 interlaced, wherein any of the conducting line 11 connecting with a plurality of gate electrodes, any of the conducting line 12 connecting with a plurality of source and drain electrodes, making the source/drain electrodes of adjacent transistors relative to each other. Another example is the array shown in FIG. 1B, formed by the conducting lines 13, 14, and the conductors 15, with the conducting lines 13 and 14 interlaced with each other; the salient of the conducting line 13, the conducting line 14, along with the conductor 15 next to the intersecting part of the conducting line 13 and 14, forming a transistor, and the conducting lines 13, 14 and the conductors 15 normally independent (i.e., to be formed separately) in order to enable each transistor to work independently.
In the fabrication of electronic components, it is normally separating the substrate 16 into a plurality of cells 17, using masks to form electronic components in a certain cell 17, repeating the procedure above for other cells 17, cutting the substrate 16, and finally packaging each cell 17 individually. Obviously, masks being used to transfer the patterns needed (for example, the pattern of a gate, a drain or a source electrode) onto the cells 17, the properties of the electronic components forming in each cell 17 will be different if the alignment of the masks is not precise, wherein the alignment error may arise from the error of the same mask aligned with different cell 17 incorrectly or different masks aligned with the same cell 17 inexactly.
To see how this could happen especially when many masks needed, take the case shown in FIG. 1B for example. If the alignment error of the mask of the gate, the drain, and the source electrode in separate cells 17 are different, as shown in FIG. 1C to 1H, the overlap between the gate and the drain electrode will be different in separate cells 17, resulting in different gate-drain capacitors (Cgd) and/or gate-source capacitors (Cgs), and therefore different properties of the transistors in separate cells 17. If the transistor array as shown in these figures controls the pixel array of a display panel, for example, the different capacitors among the transistors will cause inhomogeneous brightness in separate areas of the display panel even the tone is setting the same, namely, the spot mura.
To solve the problem, a direct solution is to align more precisely at each time that the error is small enough to be neglected, but this raises the cost and technology level needed. Hence, the well-known art normally solves the problem from another respect: to modify the pattern of the gate, the drain, and the source electrode such that the variation resulted from the alignment error is small enough to be neglected. For example, increase the area of the gate electrode to increase the gate electrode capacitor (Cs), to reduce the variation of the transistor operating voltage involved with the different gate-drain and gate-source capacitors; or modify the pattern of the drain electrode to reduce the variation of the gate-drain capacitor.
Whereas the well known art is either to increase the area of the transistor, which is contravening to lightness and smallness, or to reduce the variation to some extent that is not satisfactory. Accordingly it is necessary to modify further the layout of the transistor array shown in FIG. 1B to assure the properties of the transistors not affected by alignment error.